1. Field of the Invention
The present invention relates to vertical field effect transistors and, particularly, to the contact structure of a vertical metal oxide semiconductor field effect transistor (MOSFET).
2. Description of Related Art
Vertical MOSFETs have been used for various purposes. FIG. 10 shows the structure of a conventional MOSFET disclosed in Japanese Unexamined Patent Publication No. 2003-318396, for example, which illustrates a plan view of the layer including an N+ source layer 209. FIG. 11A is a sectional view along line XIA-XIA of FIG. 10A, and FIG. 11B is a sectional view along line XIB-XIB of FIG. 10B. In this MOSFET, a P− base layer 203 and the N+ source layer 209 are successively formed on an N− epitaxial layer 202, which is formed on the surface of an N+ silicon substrate 201. Further, a trench 205 is formed to penetrate through the P− base layer 203 and reach the N− epitaxial layer 202, and a gate oxide film 206 and a polysilicon 207 are embedded in the trench 205.
An interlayer oxide film 208 is formed on the polysilicon 207 which serves as a gate electrode. A contact hole 210 with a given depth that penetrates through the N+ source layer 209 to reach the P− base layer 203 is made between adjacent trench gates. A P+ base contact layer 204 is formed immediately beneath the contact hole 210. A trench contact 211 is deposited in the contact hole 210, and a source electrode 212 is formed on its surface. A drain electrode 213 is formed on the rear surface of the N+ silicon substrate 201.
An application of a vertical MOSFET is recently found in a DC/DC converter of a small personal computer (PC), which requires high speed processing. It is important in a vertical MOSFET used in such an application to reduce parasitic capacitance. Thus, some techniques increase a cell size in order to reduce a total area of a gate oxide film.
In a MOSFET with a relatively large cell, reducing a source length L requires increasing the size of the trench contact 211. If the large trench contact 211 is formed by filling aluminum (Al), for example, one side of the aperture size needs to be 1.5 μm or more.
Since the contact hole 210 is relatively large in the conventional MOSFET with a relatively large cell, it is easy to fill the contact hole 210 uniformly with Al without any space. However, if the cell size is 3 to 4 μm or smaller, the contact hole 210 is also small. Thus, the contact hole 210 cannot be filled with Al, and a void 214 appears in the upper central part of the contact hole 210, causing contact resistance to increase.
In order to prevent this problem from occurring, tungsten (W) is used as the trench contact 211 to be filled into the relatively small contact hole 210. However, in the case of using W as the material of the trench contact 211, even if the contact hole 210 is relatively small, if the aperture diameter of the trench contact 211 is larger than 1.2 μm, for example, it is difficult to fill the contact hole 210 completely with W in one process, and a depressed part is created in the upper surface. If the source electrode 212 is formed with Al when the depressed part exists, the source electrode 212 has a void 214 or becomes uneven as shown in FIG. 11B, which causes contact resistance to increase.
On the other hand, if the sizes of the contact hole 210 and the trench contact 211 are reduced with respect to the cell size as shown in FIGS. 12A and 12B, the source length L increases, which raises the need for designing a drain-source withstand voltage and a threshold voltage for each cell size, which decreases design efficiency. Further, if the source length L increases, the parasitic resistance of the N+ source layer 209 and the P− base layer 203 increases accordingly. If the voltage generated in the parasitic resistor of the P− base layer 203 increases when an applied voltage exceeds the drain-source withstand voltage and avalanche current flows, a parasitic bipolar transistor composed of the N− epitaxial layer 202, the P− base layer 203, and the N+ source layer 209 operates. Thus, the voltage generated in the parasitic resistor corresponds to a base-emitter voltage of the parasitic bipolar transistor. If the parasitic bipolar transistor operates, the avalanche current increases and the MOSFET is subject to breakdown.
Further, if the size of the trench contact 211 is reduced with respect to the cell size, it is difficult to contact the trench contact 211 and the N+ source layer 209 if the N+ source layer 209 is divided by an area 216 where the N+ source layer 209 is not formed for higher avalanche resistance (for example, Japanese Patent No. 2903452 and No. 3099917) as shown in FIG. 13.